Implemented PIC

src/kernel/arch/i686/isr.c

@@ -3,6 +3,7 @@
 #include "../../stdio.h"
 #include "idt.h"
 #include "io.h"
+#include "pic.h"
 
 static isr_handler g_isr_handlers[256];
 
@@ -46,6 +47,8 @@ void i686_isr_initialize_gates();
 void i686_isr_initialize(){
     i686_isr_initialize_gates();
 
+    i686_pic_initialize();
+
     for(int i = 0; i < 256; i++){
         i686_idt_enable_gate(i);
     }

src/kernel/arch/i686/pic.c

@@ -0,0 +1,31 @@
+#include "pic.h"
+#include "io.h"
+
+void i686_pic_initialize(){
+    uint8_t pic1_mask;
+    uint8_t pic2_mask;
+
+    // Save PIC masks
+    pic1_mask = i686_inb(PIC1_DATA_PORT);
+    pic2_mask = i686_inb(PIC2_DATA_PORT);
+
+    // ICW1: Initialize/reset PICs
+    i686_outb(PIC1_CMD_PORT, 0x11); // PIC1
+    i686_outb(PIC2_CMD_PORT, 0x11); // PIC2
+
+    // ICW2: Remap IRQs
+    i686_outb(PIC1_DATA_PORT, 0x20); // PIC1 remapped to 0x20 (32)
+    i686_outb(PIC2_DATA_PORT, 0x28); // PIC2 remapped to 0x28 (40)
+
+    // ICW3: Cascade settings
+    i686_outb(PIC1_DATA_PORT, 0x04); // PIC1 is told that slave PIC is at IRQ2
+    i686_outb(PIC2_DATA_PORT, 0x02); // PIC2 has cascade identity 2
+
+    // ICW4: Env info
+    i686_outb(PIC1_DATA_PORT, 0x01); // PIC1 on 8086/88 mode
+    i686_outb(PIC2_DATA_PORT, 0x01); // PIC2 on 8086/88 mode
+
+    // Restore PIC masks
+    i686_outb(PIC1_DATA_PORT, pic1_mask);
+    i686_outb(PIC2_DATA_PORT, pic2_mask);
+}

src/kernel/arch/i686/pic.h

@@ -0,0 +1,8 @@
+#pragma once
+
+#define PIC1_CMD_PORT 0x20
+#define PIC1_DATA_PORT 0x21
+#define PIC2_CMD_PORT 0xA0
+#define PIC2_DATA_PORT 0xA1
+
+void i686_pic_initialize();

src/kernel/entry.asm

@@ -23,6 +23,8 @@ mboot:
     dd MULTIBOOT_CHECKSUM
 
 call_kmain:
+    ; Enable interrupts
+    sti
     ; Call kernel
     call kmain
     ; If on qemu, shutdown