réplica de
https://github.com/Arnau478/quark.git
synced 2024-05-06 17:36:29 +02:00
Created DMA driver
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94
src/kernel/arch/i686/dma.c
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94
src/kernel/arch/i686/dma.c
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@ -0,0 +1,94 @@
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#include <stdint.h>
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#include "dma.h"
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#include "io.h"
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void i686_dma_set_address(uint8_t channel, uint16_t addr){
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if(channel > 8) return;
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uint16_t port = 0;
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switch(channel){
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case 0: port = i686_DMA0_CHAN0_ADDR_REG; break;
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case 1: port = i686_DMA0_CHAN1_ADDR_REG; break;
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case 2: port = i686_DMA0_CHAN2_ADDR_REG; break;
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case 3: port = i686_DMA0_CHAN3_ADDR_REG; break;
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case 4: port = i686_DMA1_CHAN4_ADDR_REG; break;
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case 5: port = i686_DMA1_CHAN5_ADDR_REG; break;
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case 6: port = i686_DMA1_CHAN6_ADDR_REG; break;
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case 7: port = i686_DMA1_CHAN7_ADDR_REG; break;
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}
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i686_outw(port, addr);
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}
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void i686_dma_set_count(uint8_t channel, uint16_t count){
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if(channel > 8) return;
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uint16_t port = 0;
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switch(channel){
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case 0: port = i686_DMA0_CHAN0_COUNT_REG; break;
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case 1: port = i686_DMA0_CHAN1_COUNT_REG; break;
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case 2: port = i686_DMA0_CHAN2_COUNT_REG; break;
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case 3: port = i686_DMA0_CHAN3_COUNT_REG; break;
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case 4: port = i686_DMA1_CHAN4_COUNT_REG; break;
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case 5: port = i686_DMA1_CHAN5_COUNT_REG; break;
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case 6: port = i686_DMA1_CHAN6_COUNT_REG; break;
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case 7: port = i686_DMA1_CHAN7_COUNT_REG; break;
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}
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i686_outw(port, count);
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}
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void i686_dma_set_external_page_register(uint8_t reg, uint8_t val){
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uint16_t port = 0;
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switch(reg){
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case 1: port = i686_DMA_PAGE_CHAN1_ADDRBYTE2; break;
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case 2: port = i686_DMA_PAGE_CHAN2_ADDRBYTE2; break;
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case 3: port = i686_DMA_PAGE_CHAN3_ADDRBYTE2; break;
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// 4 is not valid
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case 5: port = i686_DMA_PAGE_CHAN5_ADDRBYTE2; break;
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case 6: port = i686_DMA_PAGE_CHAN6_ADDRBYTE2; break;
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case 7: port = i686_DMA_PAGE_CHAN7_ADDRBYTE2; break;
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default: return;
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}
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}
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void i686_dma_set_mode(uint8_t channel, uint8_t mode){
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int dma = (channel < 4) ? 0 : 1;
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int chan = (dma == 0) ? channel : channel-4;
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i686_dma_mask_channel(channel);
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i686_outb((channel < 4) ? i686_DMA0_MODE_REG : i686_DMA1_MODE_REG, chan | mode);
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i686_dma_unmask_all(dma);
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}
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void i686_dma_set_read(uint8_t channel){
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i686_dma_set_mode(channel, i686_DMA_MODE_READ_TRANSFER | i686_DMA_MODE_TRANSFER_SINGLE | i686_DMA_MODE_MASK_AUTO);
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}
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void i686_dma_set_write(uint8_t channel){
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i686_dma_set_mode(channel, i686_DMA_MODE_WRITE_TRANSFER | i686_DMA_MODE_TRANSFER_SINGLE | i686_DMA_MODE_MASK_AUTO);
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}
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void i686_dma_mask_channel(uint8_t channel){
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if(channel <= 4) i686_outb(i686_DMA0_CHANMASK_REG, (1 << (channel-1)));
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else i686_outb(i686_DMA1_CHANMASK_REG, (1 << (channel-5)));
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}
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void i686_dma_unmask_channel(uint8_t channel){
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i686_outb(channel <= 4 ? i686_DMA0_CHANMASK_REG : i686_DMA1_CHANMASK_REG, channel);
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}
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void i686_dma_reset_flipflop(int dma){
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if(dma > 2) return;
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i686_outb((dma == 0) ? i686_DMA0_CLEARBYTE_FLIPFLOP_REG : i686_DMA1_CLEARBYTE_FLIPFLOP_REG, 0xFF);
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}
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void i686_dma_reset(int dma){
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i686_outb(i686_DMA0_TEMP_REG, 0xFF);
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}
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void i686_dma_unmask_all(int dma){
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i686_outb(i686_DMA1_UNMASK_ALL_REG, 0xFF);
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}
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85
src/kernel/arch/i686/dma.h
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src/kernel/arch/i686/dma.h
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#pragma once
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#include <stdint.h>
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#define i686_DMA0_STATUS_REG 0x08
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#define i686_DMA0_COMMAND_REG 0x08
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#define i686_DMA0_REQUEST_REG 0x09
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#define i686_DMA0_CHANMASK_REG 0x0A
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#define i686_DMA0_MODE_REG 0x0B
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#define i686_DMA0_CLEARBYTE_FLIPFLOP_REG 0x0C
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#define i686_DMA0_TEMP_REG 0x0D
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#define i686_DMA0_MASTER_CLEAR_REG 0x0D
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#define i686_DMA0_CLEAR_MASK_REG 0x0E
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#define i686_DMA0_MASK_REG 0x0F
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#define i686_DMA0_CHAN0_ADDR_REG 0x00
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#define i686_DMA0_CHAN0_COUNT_REG 0x01
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#define i686_DMA0_CHAN1_ADDR_REG 0x02
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#define i686_DMA0_CHAN1_COUNT_REG 0x03
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#define i686_DMA0_CHAN2_ADDR_REG 0x04
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#define i686_DMA0_CHAN2_COUNT_REG 0x05
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#define i686_DMA0_CHAN3_ADDR_REG 0x06
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#define i686_DMA0_CHAN3_COUNT_REG 0x07
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#define i686_DMA1_STATUS_REG 0xD0
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#define i686_DMA1_COMMAND_REG 0xD0
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#define i686_DMA1_REQUEST_REG 0xD2
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#define i686_DMA1_CHANMASK_REG 0xD4
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#define i686_DMA1_MODE_REG 0xD6
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#define i686_DMA1_CLEARBYTE_FLIPFLOP_REG 0xD8
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#define i686_DMA1_INTER_REG 0xDA
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#define i686_DMA1_UNMASK_ALL_REG 0xDC
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#define i686_DMA1_MASK_REG 0xDE
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#define i686_DMA1_CHAN4_ADDR_REG 0xC0
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#define i686_DMA1_CHAN4_COUNT_REG 0xC2
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#define i686_DMA1_CHAN5_ADDR_REG 0xC4
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#define i686_DMA1_CHAN5_COUNT_REG 0xC6
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#define i686_DMA1_CHAN6_ADDR_REG 0xC8
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#define i686_DMA1_CHAN6_COUNT_REG 0xCA
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#define i686_DMA1_CHAN7_ADDR_REG 0xCC
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#define i686_DMA1_CHAN7_COUNT_REG 0xCE
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#define i686_DMA_PAGE_EXTRA0 0x80
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#define i686_DMA_PAGE_CHAN2_ADDRBYTE2 0x81
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#define i686_DMA_PAGE_CHAN3_ADDRBYTE2 0x82
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#define i686_DMA_PAGE_CHAN1_ADDRBYTE2 0x83
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#define i686_DMA_PAGE_EXTRA1 0x84
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#define i686_DMA_PAGE_EXTRA2 0x85
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#define i686_DMA_PAGE_EXTRA3 0x86
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#define i686_DMA_PAGE_CHAN6_ADDRBYTE2 0x87
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#define i686_DMA_PAGE_CHAN7_ADDRBYTE2 0x88
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#define i686_DMA_PAGE_CHAN5_ADDRBYTE2 0x89
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#define i686_DMA_PAGE_EXTRA4 0x8C
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#define i686_DMA_PAGE_EXTRA5 0x8D
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#define i686_DMA_PAGE_EXTRA6 0x8E
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#define i686_DMA_PAGE_DRAM_REFRESH 0x8F
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#define i686_DMA_CMD_MASK_MEMTOMEM 0x01
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#define i686_DMA_CMD_MASK_CHAN0ADDRHOLD 0x02
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#define i686_DMA_CMD_MASK_ENABLE 0x04
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#define i686_DMA_CMD_MASK_TIMING 0x08
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#define i686_DMA_CMD_MASK_PRIORITY 0x10
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#define i686_DMA_CMD_MASK_WRITESEL 0x20
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#define i686_DMA_CMD_MASK_DREQ 0x40
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#define i686_DMA_CMD_MASK_DACK 0x80
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#define i686_DMA_MODE_MASK_SEL 0x03
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#define i686_DMA_MODE_MASK_TRA 0x0C
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#define i686_DMA_MODE_MASK_TEST 0x00
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#define i686_DMA_MODE_READ_TRANSFER 0x04
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#define i686_DMA_MODE_WRITE_TRANSFER 0x08
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#define i686_DMA_MODE_MASK_AUTO 0x10
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#define i686_DMA_MODE_MASK_IDEC 0x20
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#define i686_DMA_MODE_MASK 0xC0
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#define i686_DMA_MODE_TRANSFER_ON_DEMAND 0x00
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#define i686_DMA_MODE_TRANSFER_SINGLE 0x40
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#define i686_DMA_MODE_TRANSFER_BLOCK 0x80
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#define i686_DMA_MODE_TRANSFER_CASCADE 0xC0
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void i686_dma_set_address(uint8_t channel, uint16_t addr);
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void i686_dma_set_count(uint8_t channel, uint16_t count);
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void i686_dma_set_external_page_register(uint8_t reg, uint8_t val);
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void i686_dma_set_mode(uint8_t channel, uint8_t mode);
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void i686_dma_set_read(uint8_t channel);
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void i686_dma_set_write(uint8_t channel);
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void i686_dma_mask_channel(uint8_t channel);
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void i686_dma_unmask_channel(uint8_t channel);
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void i686_dma_reset_flipflop(int dma);
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void i686_dma_reset(int dma);
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void i686_dma_unmask_all(int dma);
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#include "fdc.h"
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#include "isr.h"
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#include "io.h"
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#include "dma.h"
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#include "../../lib/time.h"
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#include "../../lib/debug.h"
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@ -20,7 +21,7 @@ static inline void wait_irq(){
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void i686_fdc_initialize_dma(){
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i686_outb(0x0A, 0x06); // Mask DMA channel 2
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i686_outb(0xD8, 0xFF); // Reset master flip-flop
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i686_outw(0x04, 0x1000); // Address = 0x1000
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i686_outw(0x04, i686_FDC_DMA_BUFFER); // Address = 0x1000
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i686_outb(0xD8, 0xFF); // Reset master flip-flop
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i686_outb(0x05, 0xFF); // Count to 0x23FF (bytes in 2.5" floppy disk track)
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i686_outb(0x05, 0x23);
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@ -97,6 +98,9 @@ int i686_fdc_motor(bool b){
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void i686_fdc_read_sector_imp(uint8_t head, uint8_t track, uint8_t sector){
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uint32_t st0, cyl;
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// Initialize the DMA
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i686_dma_initialize_floppy((uint8_t *)i686_FDC_DMA_BUFFER, 512);
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// Set DMA for read
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i686_fdc_dma_read();
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@ -239,3 +243,17 @@ void i686_fdc_initialize(){
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// Set drive info
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i686_fdc_drive_data(13, 1, 0x0F, true);
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}
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void i686_dma_initialize_floppy(uint8_t *buffer, unsigned length){
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i686_dma_reset(1);
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i686_dma_mask_channel(i686_FDC_DMA_CHANNEL);
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i686_dma_reset_flipflop(1);
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i686_dma_set_address(i686_FDC_DMA_CHANNEL, (unsigned)buffer);
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i686_dma_reset_flipflop(1);
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i686_dma_set_count(i686_FDC_DMA_CHANNEL, length);
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i686_dma_set_read(i686_FDC_DMA_CHANNEL);
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i686_dma_unmask_all(1);
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}
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@ -48,6 +48,8 @@
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#define i686_FDC_SECTOR_DTL_512 2
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#define i686_FDC_SECTOR_DTL_1024 4
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#define i686_FDC_SECTORS_PER_TRACK 18
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#define i686_FDC_DMA_BUFFER 0x1000
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#define i686_FDC_DMA_CHANNEL 2
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void i686_fdc_initialize_dma();
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void i686_fdc_dma_read();
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@ -68,3 +70,4 @@ void i686_fdc_enable();
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void i686_fdc_reset();
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void i686_fdc_set_working_drive(int drive);
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void i686_fdc_initialize();
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void i686_dma_initialize_floppy(uint8_t *buffer, unsigned length);
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