réplica de
https://github.com/Arnau478/quark.git
synced 2024-05-19 12:26:30 +02:00
260 líneas
6,6 KiB
C
260 líneas
6,6 KiB
C
#include <stdbool.h>
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#include "fdc.h"
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#include "isr.h"
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#include "io.h"
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#include "dma.h"
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#include "../../lib/time.h"
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#include "../../lib/debug.h"
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static volatile bool g_fdc_irq = false;
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static int g_curr_drive = 0;
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static void i686_fdc_irq(registers *regs){
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g_fdc_irq = true;
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}
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static inline void wait_irq(){
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while(!g_fdc_irq); // Wait until g_fdc_irq is true
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g_fdc_irq = false; // Then reset it to false
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}
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void i686_fdc_initialize_dma(){
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i686_outb(0x0A, 0x06); // Mask DMA channel 2
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i686_outb(0xD8, 0xFF); // Reset master flip-flop
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i686_outw(0x04, i686_FDC_DMA_BUFFER); // Address = 0x1000
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i686_outb(0xD8, 0xFF); // Reset master flip-flop
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i686_outb(0x05, 0xFF); // Count to 0x23FF (bytes in 2.5" floppy disk track)
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i686_outb(0x05, 0x23);
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i686_outb(0x80, 0x00); // External page register = 0
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i686_outb(0x0A, 0x02); // Unmask DMA channel 2
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}
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void i686_fdc_dma_read(){
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i686_outb(0x0A, 0x06); // Mask DMA channel 2
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i686_outb(0x0B, 0x56); // single transfer, address increment, autoinit, read, channel 2
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i686_outb(0x0A, 0x02); // Unmask DMA channel 2
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}
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void i686_fdc_dma_write(){
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i686_outb(0x0A, 0x06); // Mask DMA channel 2
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i686_outb(0x0B, 0x5A); // single transfer, address increment, autoinit, write, channel 2
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i686_outb(0x0A, 0x02); // Unmask DMA channel 2
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}
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uint8_t i686_fdc_msr_read(){
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return i686_inb(i686_FDC_MSR);
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}
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void i686_fdc_send_cmd(uint8_t cmd){
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while(!(i686_fdc_msr_read() & i686_FDC_MSR_DATAREG));
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i686_outb(i686_FDC_FIFO, cmd);
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}
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uint8_t i686_fdc_read_data(){
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while(!(i686_fdc_msr_read() & i686_FDC_MSR_DATAREG));
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return i686_inb(i686_FDC_FIFO);
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}
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void i686_fdc_write_ccr(uint8_t v){
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i686_outb(i686_FDC_CTRL, v);
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}
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void i686_fdc_drive_data(uint32_t stepr, uint32_t loadt, uint32_t unloadt, bool dma){
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uint32_t data = 0;
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i686_fdc_send_cmd(i686_FDC_CMD_SPECIFY);
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data = ((stepr & 0xF) << 4) | (unloadt & 0xF);
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i686_fdc_send_cmd(data);
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data = loadt << 1 | dma ? 1 : 0; // Ensure dma is a 0/1 bool
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i686_fdc_send_cmd(data);
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}
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void i686_fdc_check_int(uint32_t *st0, uint32_t *cyl){
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i686_fdc_send_cmd(i686_FDC_CMD_CHECK_INT);
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*st0 = i686_fdc_read_data();
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*cyl = i686_fdc_read_data();
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}
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int i686_fdc_motor(bool b){
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if(g_curr_drive > 3) return -2;
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uint32_t motor = 0;
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switch(g_curr_drive){
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case 0: motor = i686_FDC_DOR_DRIVE0_MOTOR; break;
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case 1: motor = i686_FDC_DOR_DRIVE1_MOTOR; break;
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case 2: motor = i686_FDC_DOR_DRIVE2_MOTOR; break;
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case 3: motor = i686_FDC_DOR_DRIVE3_MOTOR; break;
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}
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if(b) i686_outb(i686_FDC_DOR, g_curr_drive | motor | i686_FDC_DOR_RESET | i686_FDC_DOR_DMA);
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else i686_outb(i686_FDC_DOR, i686_FDC_DOR_RESET);
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// Give the motor some time
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sleep(20);
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}
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void i686_fdc_read_sector_imp(uint8_t head, uint8_t track, uint8_t sector){
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uint32_t st0, cyl;
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// Initialize the DMA
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i686_dma_initialize_floppy((uint8_t *)i686_FDC_DMA_BUFFER, 512);
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// Set DMA for read
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i686_fdc_dma_read();
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// Read a sector
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i686_fdc_send_cmd(i686_FDC_CMD_READ_SECT | i686_FDC_CMD_EXT_MULTITRACK | i686_FDC_CMD_EXT_SKIP | i686_FDC_CMD_EXT_DENSITY);
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i686_fdc_send_cmd(head << 2 | g_curr_drive);
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i686_fdc_send_cmd(track);
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i686_fdc_send_cmd(head);
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i686_fdc_send_cmd(sector);
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i686_fdc_send_cmd(i686_FDC_SECTOR_DTL_512);
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i686_fdc_send_cmd((sector + 1) >= i686_FDC_SECTORS_PER_TRACK ? i686_FDC_SECTORS_PER_TRACK : sector + 1);
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i686_fdc_send_cmd(i686_FDC_GAP3_3_5);
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i686_fdc_send_cmd(0xFF);
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// Wait for IRQ
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wait_irq();
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// Read output
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for(int i = 0; i < 7; i++) i686_fdc_read_data();
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// Tell the FDC we are done
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i686_fdc_check_int(&st0, &cyl);
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}
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static void lba_to_chs(int lba, int *head, int *track, int *sector){
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*head = (lba % (i686_FDC_SECTORS_PER_TRACK * 2)) / i686_FDC_SECTORS_PER_TRACK;
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*track = lba / (i686_FDC_SECTORS_PER_TRACK * 2);
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*sector = lba % i686_FDC_SECTORS_PER_TRACK + 1;
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}
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uint8_t *i686_fdc_read_sector(int lba){
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if(g_curr_drive > 3) return 0;
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// Convert LBA to CHS
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int head = 0, track = 0, sector = 1;
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lba_to_chs(lba, &head, &track, §or);
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// Turn on motor and seek
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i686_fdc_motor(true);
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if(i686_fdc_seek(track, head) != 0) return 0;
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// Read and turn off motor
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i686_fdc_read_sector_imp(head, track, sector);
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i686_fdc_motor(false);
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return (uint8_t *)0x1000;
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}
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int i686_fdc_calibrate(uint32_t drive){
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uint32_t st0, cyl;
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if(drive > 3) return -2;
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i686_fdc_motor(true);
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for(int i = 0; i < 10; i++){
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// Send command
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i686_fdc_send_cmd(i686_FDC_CMD_CALIBRATE);
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i686_fdc_send_cmd(drive);
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wait_irq();
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i686_fdc_check_int(&st0, &cyl);
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if(!cyl){
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i686_fdc_motor(false);
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return 0;
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}
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}
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i686_fdc_motor(false);
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return -1;
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}
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int i686_fdc_seek(uint32_t cyl, uint32_t head){
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uint32_t st0, cyl0;
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if(g_curr_drive > 3) return -2;
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for(int i = 0; i < 10; i++){
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// Send the command
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i686_fdc_send_cmd(i686_FDC_CMD_SEEK);
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i686_fdc_send_cmd(head << 2 | g_curr_drive);
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i686_fdc_send_cmd(cyl);
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// Wait for the results
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wait_irq();
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i686_fdc_check_int(&st0, &cyl0);
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// Found?
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if(cyl0 == cyl) return 0;
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}
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return -1;
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}
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void i686_fdc_disable(){
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i686_outb(i686_FDC_DOR, 0);
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}
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void i686_fdc_enable(){
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i686_outb(i686_FDC_DOR, i686_FDC_DOR_RESET | i686_FDC_DOR_DMA);
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}
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void i686_fdc_reset(){
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uint32_t st0, cyl;
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// Reset the controller
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i686_fdc_disable();
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i686_fdc_enable();
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wait_irq();
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// CHECK_INT to all drives
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for(int i = 0; i < 4; i++) i686_fdc_check_int(&st0, &cyl);
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// 500kb/s
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i686_fdc_write_ccr(0);
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// steprate = 3ms, unload time = 240ms, load time = 16ms, dma = true
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i686_fdc_drive_data(3, 16, 240, true);
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// Calibrate the disk
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i686_fdc_calibrate(g_curr_drive);
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}
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void i686_fdc_set_working_drive(int drive){
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if(drive < 4) g_curr_drive = drive;
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}
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void i686_fdc_initialize(){
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debug_printf("[FDC] Initializing\n");
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// Setup IRQ
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i686_isr_register_handler(IRQ(6), i686_fdc_irq);
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// Initialize DMA
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i686_fdc_initialize_dma();
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// Reset FDC
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i686_fdc_reset();
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// Set drive info
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i686_fdc_drive_data(13, 1, 0x0F, true);
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}
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void i686_dma_initialize_floppy(uint8_t *buffer, unsigned length){
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i686_dma_reset(1);
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i686_dma_mask_channel(i686_FDC_DMA_CHANNEL);
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i686_dma_reset_flipflop(1);
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i686_dma_set_address(i686_FDC_DMA_CHANNEL, (unsigned)buffer);
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i686_dma_reset_flipflop(1);
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i686_dma_set_count(i686_FDC_DMA_CHANNEL, length);
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i686_dma_set_read(i686_FDC_DMA_CHANNEL);
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i686_dma_unmask_all(1);
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}
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