APIC timer driver

This commit is contained in:
Arnau Camprubí 2022-06-18 19:19:03 +02:00
pare d5a18de997
commit e93cf7db3c
S'han modificat 6 arxius amb 31 adicions i 3 eliminacions

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@ -57,6 +57,14 @@ void i686_isr_initialize(){
void __attribute__((cdecl)) i686_isr_handler(registers *regs){
if(g_isr_handlers[regs->interrupt] != NULL){
g_isr_handlers[regs->interrupt](regs);
// Send EOI to PIC if necessary
if(regs->interrupt >= PIC1_VEC_OFFSET && regs->interrupt < PIC1_VEC_OFFSET+8){
i686_outb(PIC1_CMD_PORT, PIC_EOI);
}
else if(regs->interrupt >= PIC2_VEC_OFFSET && regs->interrupt < PIC2_VEC_OFFSET+8){
i686_outb(PIC2_CMD_PORT, PIC_EOI);
}
}
else if(regs->interrupt >= 32){
printf("Unhandled interrupt %i\n", regs->interrupt);

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@ -14,8 +14,8 @@ void i686_pic_initialize(){
i686_outb(PIC2_CMD_PORT, 0x11); // PIC2
// ICW2: Remap IRQs
i686_outb(PIC1_DATA_PORT, 0x20); // PIC1 remapped to 0x20 (32)
i686_outb(PIC2_DATA_PORT, 0x28); // PIC2 remapped to 0x28 (40)
i686_outb(PIC1_DATA_PORT, PIC1_VEC_OFFSET); // PIC1 remapped to PIC1_VEC_OFFSET
i686_outb(PIC2_DATA_PORT, PIC2_VEC_OFFSET); // PIC2 remapped to PIC2_VEC_OFFSET
// ICW3: Cascade settings
i686_outb(PIC1_DATA_PORT, 0x04); // PIC1 is told that slave PIC is at IRQ2

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@ -5,4 +5,9 @@
#define PIC2_CMD_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
#define PIC1_VEC_OFFSET 0x20
#define PIC2_VEC_OFFSET 0x28
#define PIC_EOI 0x20
void i686_pic_initialize();

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@ -0,0 +1,11 @@
#include "timer.h"
#include "../arch/i686/isr.h"
#include "../stdio.h"
static void timer_handler(registers *regs){
printf("TICK\n");
}
void timer_initialize(){
i686_isr_register_handler(IRQ(0), timer_handler);
}

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@ -0,0 +1,3 @@
#pragma once
void timer_initialize();

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@ -1,13 +1,14 @@
#include <stdint.h>
#include "stdio.h"
#include "hal/hal.h"
#include "drivers/timer.h"
void __attribute__((cdecl)) kmain(uint64_t magic, uint64_t addr){
hal_initialize();
timer_initialize();
puts("\x1b[33mWARNING\x1b[0m");
printf(": amazing %s ahead!\n", "math");
printf("%i+%i=%i\n", 1, 1, 2);
printf("0/0=%i", 0/0);
for(;;);
}